1. Field of the Invention
The present invention relates generally to multi-chip modules and, particularly, to multi-chip modules including a first semiconductor die with one or more other semiconductor dice connected directly thereto in a flip-chip fashion. The present invention also relates to methods for assembling these multi-chip modules. In addition, the present invention relates to semiconductor device packages including the inventive multi-chip modules and to methods for forming such packages.
2. State of the Art
Accompanying the trend toward manufacturing computers and other electronic devices of ever increasing speed and ever decreasing size is the need for semiconductor device components of ever increasing capabilities and, thus, having an increased number of features that consume the same or a lesser amount of space.
Multi-chip modules are one example of an approach that has been taken in the semiconductor device industry to increase the feature density of semiconductor devices. Known multi-chip modules typically include a plurality of semiconductor dice that may be electrically connected to one another indirectly by way of carrier substrates to which each of the dice are electrically connected.
U.S. Pat. No. 5,914,535 (hereinafter xe2x80x9cthe ""535 Patentxe2x80x9d), issued to Brandenburg on Jun. 22, 1999, discloses a multi-chip module including a daughter board with several semiconductor dice flip-chip bonded thereto. The daughter board includes contact pads located outside of a periphery of an area where the semiconductor dice are flip-chip bonded to facilitate flip-chip connection of the multi-chip module to a mother board with the dice of the multi-chip module being located between the daughter board and the mother board.
Another type of multi-chip module is disclosed in U.S. Pat. No. 5,719,436 (hereinafter xe2x80x9cthe ""436 Pat. No. xe2x80x9d) and 5,793,101 (hereinafter xe2x80x9cthe ""101 Pat.xe2x80x9d), issued to Kuhn on Feb. 17, 1998 and Aug. 11, 1998, respectively. Both the ""436 and ""101 Patents disclose packaged multi-chip modules that include a plurality of semiconductor dice. Each package includes a substrate bearing conductive traces, to which each of the semiconductor dice are electrically connected. The semiconductor dice may be electrically connected to the substrate by way of wire bonding or flip-chip bonding. The substrate, which may comprise a flex circuit, wraps around and is supported by both surfaces of a die paddle. The conductive traces of the substrate are electrically connected to leads by bond wires. Bond pads of the semiconductor dice may also be directly electrically connected to the leads of the package.
U.S. Pat. No. RE36,613, issued to Ball on Mar. 14, 2000, discloses a multi-chip module including stacked semiconductor dice. While the dice are stacked one on top of another, they are not directly connected to one another, but rather to leads of a package including the multi-chip module.
Other types of multi-chip modules that include one or more semiconductor dice that are flip-chip bonded to a carrier are also known. None of these multi-chip modules, however, includes semiconductor dice that are directly flip-chip bonded to one another with the subsequent assembly then being flip-chip mounted to a substrate.
Keeping in mind the trend toward faster computers and other electronic devices, the use of intermediate conductive elements, such as wire bonds, and the conductive traces of carrier substrates to electrically connect the semiconductor dice of a multi-chip module is somewhat undesirable since the electrical paths of these types of connections are typically lengthy and, consequently, limit the speed with which the semiconductor dice of the multi-chip module may communicate with one another. The affects that these types of connections in conventional multi-chip modules have on the speed at which an electronic device, such as a computer, operates are particularly undesirable when one of the semiconductor dice of the multi-chip module is a microprocessor and the other semiconductor dice of the multi-chip module are semiconductor devices with which the microprocessor should quickly communicate.
The so-called system-on-a-chip (SOC) has been developed to increase the speed with which two semiconductor devices, such as a logic device (e.g., a microprocessor) and a memory device, communicate. Each of the semiconductor devices of a SOC structure are fabricated on the same substrate, providing very short connections with reduced contact resistance between two or more devices. The speed with which the two devices communicate is, therefore, increased relative to the speeds with which the separate semiconductor devices of conventional assemblies communicate.
While system-on-a-chip technology provides much quicker communication between different semiconductor devices, the fabrication processes that are used to make different types of semiconductor devices, such as logic and memory devices, differ significantly. In fact, the best processes to fabricate similar structures on different types of semiconductor devices may be very different. Moreover, the organization and locations of structures on different types of semiconductor devices may also differ significantly. Thus, it is not only difficult to merge two or more processes to facilitate the simultaneous fabrication of two or more different types of semiconductor devices on the same substrate, such simultaneous fabrication also requires process compromises for one or more of the types of semiconductor devices being fabricated, which may increase fabrication costs and decrease the performance of one or more of the different types of simultaneously fabricated semiconductor devices.
Accordingly, there is a need for a multi-chip module with increased speed of communication between the semiconductor dice thereof, the semiconductor dice of which may be fabricated by existing processes.
The present invention includes an assembly of a first semiconductor die and at least one second semiconductor die. Each second semiconductor die of the assembly is flip-chip bonded to the first semiconductor die thereof. The assembly may also include a carrier substrate configured to have the first semiconductor die connected thereto in a flip-chip fashion.
The first semiconductor die includes bond pads arranged in an array over an active surface thereof. While some of the bond pads of the first semiconductor die are arranged on the active surface thereof so as to correspond to a footprint of bond pads of each second semiconductor die, others of the bond pads of the first semiconductor die are positioned so as to be exposed laterally beyond outer peripheries of one or more second semiconductor dice upon assembly thereof with the first semiconductor die. Each of the bond pads of the first semiconductor die that corresponds to a bond pad of a second semiconductor die may be recessed relative to the active surface so as to facilitate alignment and electrical connection with conductive structures protruding from the bond pads of the second semiconductor die. Each of the other, outer bond pads of the first semiconductor die, which may also be recessed relative to the active surface, may have protruding therefrom a conductive structure. Exemplary conductive structures include, but are not limited to, balls, bumps, columns, and pillars of conductive material, such as a solder, another metal or metal alloy, a conductive epoxy, a conductor-filled epoxy, or a z-axis conductive elastomer. These conductive structures facilitate electrical connection of an assembly including the first semiconductor die to a carrier for such an assembly. The first semiconductor die may be a microprocessor die or a die of any other known semiconductor device type.
Each second semiconductor die includes an active surface with a plurality of bond pads thereon. The bond pads of each second semiconductor die may be arranged on the active surface thereof in any manner known in the art, but are preferably disposed across the surface of each second semiconductor die in an array. The bond pads of each second semiconductor die are positioned so as to align with corresponding bond pads of the first semiconductor die upon orienting the second semiconductor die with the active surface thereof facing the active surface of the first semiconductor die. The bond pads of each second semiconductor die may be recessed relative to the active surface thereof so as to at least partially receive and align conductive structures with the bond pads. Each bond pad of each second semiconductor die may have a conductive structure secured thereto and protruding therefrom so as to facilitate electrical communication between first and second semiconductor dice upon assembly and electrical connection thereof. Semiconductor devices that may be used as a second semiconductor die include, without limitation, dynamic random access memories (DRAMs), static random access memories (SRAMs), other types of memory devices, ancillary or logic devices, and other known types of semiconductor devices.
The assembly may also include an alignment structure on the active surface of the first semiconductor die. The alignment structure preferably protrudes from the active surface of the first semiconductor die and includes at least one member configured to guide at least two adjoined peripheral edges of a second semiconductor die so as to facilitate the alignment of bond pads of the second semiconductor die with corresponding bond pads of the first semiconductor die upon orientation of the first and second semiconductor dice with the active surfaces thereof facing each other. The alignment structure thereby facilitates the formation of short, reliable electrical connections between corresponding bond pads of the first and second semiconductor dice. Each member of the alignment structure is preferably formed from an electrically insulative material and may be fabricated by known processes, such as by use of a photoresist, other photoimageable polymers, stereolithographic techniques, or by forming and patterning a layer of material on the active surface of the first semiconductor die. One or more alignment structures may also, or in the alternative, be disposed on a surface of a carrier, such as a carrier substrate, to facilitate the alignment of outer bond pads of the first semiconductor die with contact pads on the surface of the carrier upon orientation of the first semiconductor die with the active surface thereof facing the surface of the carrier.
The contact pads of the carrier are arranged on a surface thereof so as to correspond with a footprint of other, outer bond pads of the first semiconductor die that are to be located laterally beyond an outer periphery of a second semiconductor die upon assembly of the second semiconductor die with the first semiconductor die. Accordingly, the contact pads of the carrier are so located as to facilitate the flip-chip type connection of the first semiconductor die to the carrier. The carrier may also include, formed in the surface thereof, at least one recess configured and located to at least partially receive a corresponding second semiconductor die.
The first semiconductor die and each second semiconductor die to be electrically connected therewith may be assembled by orienting each second semiconductor die with the bond pads thereof in alignment with corresponding bond pads of the first semiconductor die. In such orienting, the active surfaces of the first and second semiconductor dice are facing one another. Bumps or other conductive structures on bond pads of one of the first and second semiconductor dice may be received by recesses of the other of the first and second semiconductor dice to facilitate alignment and electrical connection of the corresponding bond pads of the first and second semiconductor dice. Alternatively, or in addition, the orientation of each second semiconductor die relative to the first semiconductor die may be effected by way of an alignment structure protruding from the active surface of the first semiconductor die. Once each second semiconductor die has been properly oriented relative to the first semiconductor die, corresponding bond pads of the first and second semiconductor dice may be electrically connected by way of forming flip-chip type connections utilizing the conductive structures.
The assembly of semiconductor dice flip-chip bonded to one another may then be assembled with a carrier by orienting the active surface of the first semiconductor die over the surface of the carrier, with the outer bond pads of the first semiconductor die and the corresponding contact pads of the carrier in substantial alignment. Each recess formed in the surface of the carrier may also receive the corresponding second semiconductor die during orientation of the first semiconductor die over the carrier. Again, orientation of the first semiconductor die over the carrier may be facilitated by alignment structures protruding from the surface of the carrier. Once the first semiconductor die has been properly oriented over the carrier, the outer bond pads of the first semiconductor die and the corresponding contact pads of the carrier may be electrically connected to one another by way of known flip-chip type connections.
Alternatively, the first semiconductor die, at least one second semiconductor die, and the carrier substrate may be assembled by disposing each second semiconductor die in a corresponding recess of the carrier substrate and orienting the first semiconductor die over each second semiconductor die and the carrier substrate so as to align the bond pads thereof with corresponding bond pads of each second semiconductor die and with corresponding contact pads of the carrier. Electrical connections between bond pads of the first semiconductor die and the corresponding bond pads of each second semiconductor die may be formed substantially simultaneously with the electrical connections between the outer bond pads of the first semiconductor die and the corresponding contact pads of the carrier.
Once the semiconductor dice and the carrier have been assembled, at least the electrical connections between the first semiconductor die and each second semiconductor die connected thereto, as well as the connections between the first semiconductor die and the carrier, may be protected with an encapsulant material. For example, an underfill material may be introduced between the first semiconductor die and the carrier. As another example, known encapsulation techniques, such as transfer molding or the use of glob-top encapsulant materials, may be used to substantially cover and encapsulate the first and second semiconductor dice.
Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.